The present invention generally relates to fabrication of semiconductor devices and more specifically to the alignment technology of a stepper.
With the demand of higher operational speed and versatile function for semiconductor devices, patterns formed on a surface of a semiconductor wafer such as a silicon wafer have now become extremely miniaturized. Associated with this, it is now required an extremely high-precision alignment in the photolithographic process, particularly the exposure process of semiconductor substrate conducted by using steppers.
Generally, a semiconductor device includes a semiconductor substrate carrying active elements such as a transistor and plural interconnection layers formed on such a semiconductor substrate, wherein each interconnection layer is formed of an interlayer insulation film and an interconnection pattern embedded in the interlayer insulation film.
In the fabrication process of a such a semiconductor device, alignment marks are used for achieving positional alignment between the upper and lower interconnection layers.
(Patent Reference 1) Japanese Laid Open Patent Application 2000-260702 official gazette
(Patent Reference 2) Japanese Laid Open Patent Application 2002-289507 official gazette
(Patent Reference 3) Japanese Laid-Open Patent Application 6-29183 official gazette